1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof particularly suitable for application in semiconductor memories such as DRAM and so on which comprise memory cells each including a selecting transistor and a memory capacitor.
2. Description of the Related Art
Generally, a memory cell in DRAM includes a selecting transistor having a gate, a drain and a source, and a memory capacitor having a storage node electrode connected to the source and a cell plate electrode opposing the storage node electrode through a dielectric film formed therebetween. In the DRAM constructed with the components as mentioned above, a larger surface area must be provided for the storage node electrode in order to ensure the capacitance of the memory capacitor, thereby causing necessarily a larger difference of level or height between a memory cell region and a peripheral circuit region.
To reduce the difference of level or height due to the memory capacitor, a BPSG (Boro-Phospho Silicate Glass) film, for example, is formed as an inter-layer insulating film for covering the selecting transistor and the memory capacitor after the cell plate electrode is formed. Then, this BPSG film is reflowed, and the entire surface of the BPSG film is etched back for planarization of the surface. In this processing, an end point of the etch back is determined by detecting an exposed portion of the cell plate electrode which is a top polycrystalline silicon film within the BPSG film. Subsequently, an insulating film is formed over the BPSG film to cover the exposed portion of the cell plate electrode, and then a variety of wiring films are patterned on the insulating film which has a planarized surface.
As described above, since the conventional level difference reducing method for DRAM utilizes the cell plate electrode as a stopper for the etch back, the formation of an insulating film for again covering the exposed cell plate electrode is indispensable, thus causing an increase in the number and complexity of manufacturing steps.
JP-A-7-153849 discloses an approach for reducing a difference of level in a DRAM structure. Specifically, during the manufacturing of a DRAM, a polysilicon film for dummy pattern is formed around the outer periphery of a plurality of storage node electrodes formed adjacent to each other, such that the polysilicon film for dummy pattern reduces a slope of a surface of the DRAM overlying contact holes formed in close proximity to the storage node electrodes positioned along the outer edges to reduce the difference of level.
JP-A-5-136132 discloses another approach for reducing a difference of level in a DRAM structure, wherein a first dummy layer is formed simultaneously with gate electrodes, and a second dummy layer is formed simultaneously with storage node electrodes in an area inside of the first dummy layer, during the manufacturing of a DRAM, to reduce a slope of an end surface over memory capacitors, thereby reducing the difference of level.
The approaches disclosed in JP-A-7-153849 and 5-136132, however, involve the formation of an inter-layer insulating film to bury dummy patterns thereinto, so that even although these approaches may contribute to a reduced slope, it seems to be difficult to provide sufficient planarity for the surface of the inter-layer insulating film. If sufficient planarity is not ensured for the surface of the inter-layer insulating film, halation will occur when a wiring film is patterned on the inter-layer insulating film, resulting in thinner portions in the wiring film.
JP-B-6-80667, though not directed to semiconductor devices represented by DRAM having a large difference of level between components nor intended to reduce a slope of an inter-layer insulating film over a difference of level in a device, discloses a method of forming a plurality of connection structures for simultaneously forming respective wires for connection with diffusion layers and gate electrodes on a semiconductor substrate having a rugged surface.
However, since this manufacturing method utilizes a wire located at a higher level as a stopper for etch back, the formation of an insulating film is indispensable for again covering exposed wires, in a manner similar to the aforementioned prior art example.
JP-A-9-51038 discloses the formation of a patterned polysilicon, a nitride film and so on over a redundant fuse portion through an oxide film, with the polysilicon used as a stopper for etching the nitride film or the like overlying the redundant fuse portion. Here, the redundant fuse refers to a wire which will be cut for replacing a defective memory cell with a normal memory cell, and an insulating film must be left exclusively on the redundant fuse in a thickness of approximately 200 nm to 400 nm. For this reason, the patterned polysilicon is etched away to its bottom, so that the oxide film is exposed.
However, since this manufacturing method involves forming the polysilicon pattern approximately 200 nm to 400 nm above the redundant fuse, the surfaces of the nitride film or the like cannot be planarized.